1. Field of the Invention
The present invention relates to a sequential phase-frequency detector circuit and more particularly to such a circuit using precharged logic and adapted for use in a CMOS delay-locked loop.
2. Background of the Invention
A modem, complex, high-speed CMOS VLSI chip often requires the use of multiple clock regeneration circuits to insure that all parts of the chip operate properly together. These clock regeneration circuits employ delay-locked and phase-locked loops to provide LOCAL clock signals which are synchronized to an external REFERENCE clock.
Each locked loop employs a sequential phase-frequency detector circuit to compare the REFERENCE and LOCAL signals and provides a pair of digital output signals ("UP" and "DOWN") having an ON duration proportional to a phase difference between the compared signals.
Typical sequential phase-frequency detectors are described in D. K. Jeong et al., "Design of PLL-Based Clock Generation Circuits," IEEE Journal of Solid State Circuits, vol. 22, no. 2, pp. 255-261, 1987, and in P. Jordan, "An Exclusive-Or Phase/Frequency Detector," Proc. RF Expo East, Atlantic City, N.J., Oct. 1989, pp. 223-229, Cardiff Pub.
Delay-locked and phase-locked loops using these sequential phase-frequency detectors suffer from excessive phase jitter at small phase differences. The jitter is caused by a region of low gain, known as the "dead zone," at the small phase differences, and prevents the use of the conventional detectors in systems requiring high clock frequencies. The conventional detectors also require many transistors for implementation in CMOS VLSI chips, making their use undesirable at high layout densities.
A sequential phase-frequency detector circuit using precharged CMOS logic for high frequency operation, having a minimum detectable phase difference of 40 pico-seconds, and requiting one third the transistors of the conventional circuits, is illustrated in FIG. 1. The circuit is described in H. Notani et al., "A 622-MHz CMOS Phase-Locked Loop with Precharge-type Phase Frequency Detector," 1994 IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp. 129-130.
As shown in FIG. 1, the node 1 is precharged while the input signal REF is low, and the node 2 holds its previous value. When the signal REF goes high, the node 1 is ready to be discharged. When the input signal LOC goes high, the node 1 is discharged, which makes the UP output signal low. The UP output signal is active from the rising edge of the REF signal until the rising edge of the LOC signal. In a complementary manner, the output signal DOWN is active from a rising edge of the signal LOC to a rising edge of the signal REF.
As will be seen from an examination of FIG. 1, the UP output signal cannot be asserted when the LOC signal is stuck at a high level. The Notani et al. detector works quite well when the frequency of the system-wide REFERENCE clock and the LOCAL clock are nearly the same. This will be true, for example, when the Notani et al. detector is used in a phase-locked loop having a voltage-controlled oscillator (see FIG. 2 in Notani et al.) because the voltage-controlled oscillator will adjust its frequency to follow the system-wide REFERENCE signal over a very wide range of frequencies, insuring that the LOC input does not become stuck.
When used in a delay-locked loop employing a voltage controlled delay line, on the other hand, the Notani et al. circuit fails to assert the UP control signal when the LOC input is stuck at a high level. This result occurs because the stuck LOC input permits the node 1 to discharge when the REF input goes high. The Notani et al. circuit is therefore not suitable for use in a delay locked loop in which the output of the delay line may become stuck when the delay is longer than approximately 1.5 to 2 times the clock period of the REFERENCE input. This result is common during frequency acquisition following a return from an Energy-Star.TM. mode in which the frequency of the REFERENCE signal is initially significantly less than its normal operating frequency.